 
#TITLE    'SSD2 sensor counters 0..5';
#ENGINEER 'Pekka Riihela ';
#COMPANY  'Finnish Meteorological Institute ';
#PROJECT  'ASPERA-C ';
#REVISION '1.0 11.08.1993';
#COMMENT  '';
 
 
INPUT  rd_ssd;                             "Read SSD counter
INPUT wr_ssd;                              "Dummy input as master_clk
INPUT master_clk;                          "Only for case you need it.
                                           "On this design it is not needed,
                                           "but it must define and USE.
 
INPUT sel_cntr[3];                         "Select counter for read
 
INPUT reset;
 
INPUT clk_c0;
INPUT clk_c1;
INPUT clk_c2;
INPUT clk_c3;
INPUT clk_c4;
INPUT clk_c5;                              "Counters clock inputs;
 
INPUT clr_cntrs;
 
 
OUTPUT ds_i[16] ENABLED_BY (/rd_ssd*(/sel_cntr[2]+/sel_cntr[1]));        "IO to sensor bus
 
 
NODE int_clr_cntrs DEFAULT_TO 0;
 
NODE clk_c0_a;
NODE clk_c1_a;
NODE clk_c2_a;
NODE clk_c3_a;
NODE clk_c4_a;
NODE clk_c5_a;
 
 
 
 
                             "Ripple counters
 
NODE c0_00 CLOCKED_BY clk_c0_a RESET_BY int_clr_cntrs;
NODE c0_01 CLOCKED_BY /c0_00 RESET_BY int_clr_cntrs;
NODE c0_02 CLOCKED_BY /c0_01 RESET_BY int_clr_cntrs;
NODE c0_03 CLOCKED_BY /c0_02 RESET_BY int_clr_cntrs;
NODE c0_04 CLOCKED_BY /c0_03 RESET_BY int_clr_cntrs;
NODE c0_05 CLOCKED_BY /c0_04 RESET_BY int_clr_cntrs;
NODE c0_06 CLOCKED_BY /c0_05 RESET_BY int_clr_cntrs;
NODE c0_07 CLOCKED_BY /c0_06 RESET_BY int_clr_cntrs;
NODE c0_08 CLOCKED_BY /c0_07 RESET_BY int_clr_cntrs;
NODE c0_09 CLOCKED_BY /c0_08 RESET_BY int_clr_cntrs;
NODE c0_10 CLOCKED_BY /c0_09 RESET_BY int_clr_cntrs;
NODE c0_11 CLOCKED_BY /c0_10 RESET_BY int_clr_cntrs;
NODE c0_12 CLOCKED_BY /c0_11 RESET_BY int_clr_cntrs;
NODE c0_13 CLOCKED_BY /c0_12 RESET_BY int_clr_cntrs;
NODE c0_14 CLOCKED_BY /c0_13 RESET_BY int_clr_cntrs;
NODE c0_15 CLOCKED_BY /c0_14 RESET_BY int_clr_cntrs; "Counter 0
 
NODE c1_00 CLOCKED_BY clk_c1_a RESET_BY int_clr_cntrs;
NODE c1_01 CLOCKED_BY /c1_00 RESET_BY int_clr_cntrs;
NODE c1_02 CLOCKED_BY /c1_01 RESET_BY int_clr_cntrs;
NODE c1_03 CLOCKED_BY /c1_02 RESET_BY int_clr_cntrs;
NODE c1_04 CLOCKED_BY /c1_03 RESET_BY int_clr_cntrs;
NODE c1_05 CLOCKED_BY /c1_04 RESET_BY int_clr_cntrs;
NODE c1_06 CLOCKED_BY /c1_05 RESET_BY int_clr_cntrs;
NODE c1_07 CLOCKED_BY /c1_06 RESET_BY int_clr_cntrs;
NODE c1_08 CLOCKED_BY /c1_07 RESET_BY int_clr_cntrs;
NODE c1_09 CLOCKED_BY /c1_08 RESET_BY int_clr_cntrs;
NODE c1_10 CLOCKED_BY /c1_09 RESET_BY int_clr_cntrs;
NODE c1_11 CLOCKED_BY /c1_10 RESET_BY int_clr_cntrs;
NODE c1_12 CLOCKED_BY /c1_11 RESET_BY int_clr_cntrs;
NODE c1_13 CLOCKED_BY /c1_12 RESET_BY int_clr_cntrs;
NODE c1_14 CLOCKED_BY /c1_13 RESET_BY int_clr_cntrs;
NODE c1_15 CLOCKED_BY /c1_14 RESET_BY int_clr_cntrs; "Counter 1
 
NODE c2_00 CLOCKED_BY clk_c2_a RESET_BY int_clr_cntrs;
NODE c2_01 CLOCKED_BY /c2_00 RESET_BY int_clr_cntrs;
NODE c2_02 CLOCKED_BY /c2_01 RESET_BY int_clr_cntrs;
NODE c2_03 CLOCKED_BY /c2_02 RESET_BY int_clr_cntrs;
NODE c2_04 CLOCKED_BY /c2_03 RESET_BY int_clr_cntrs;
NODE c2_05 CLOCKED_BY /c2_04 RESET_BY int_clr_cntrs;
NODE c2_06 CLOCKED_BY /c2_05 RESET_BY int_clr_cntrs;
NODE c2_07 CLOCKED_BY /c2_06 RESET_BY int_clr_cntrs;
NODE c2_08 CLOCKED_BY /c2_07 RESET_BY int_clr_cntrs;
NODE c2_09 CLOCKED_BY /c2_08 RESET_BY int_clr_cntrs;
NODE c2_10 CLOCKED_BY /c2_09 RESET_BY int_clr_cntrs;
NODE c2_11 CLOCKED_BY /c2_10 RESET_BY int_clr_cntrs;
NODE c2_12 CLOCKED_BY /c2_11 RESET_BY int_clr_cntrs;
NODE c2_13 CLOCKED_BY /c2_12 RESET_BY int_clr_cntrs;
NODE c2_14 CLOCKED_BY /c2_13 RESET_BY int_clr_cntrs;
NODE c2_15 CLOCKED_BY /c2_14 RESET_BY int_clr_cntrs; "Counter 2
 
NODE c3_00 CLOCKED_BY clk_c3_a RESET_BY int_clr_cntrs;
NODE c3_01 CLOCKED_BY /c3_00 RESET_BY int_clr_cntrs;
NODE c3_02 CLOCKED_BY /c3_01 RESET_BY int_clr_cntrs;
NODE c3_03 CLOCKED_BY /c3_02 RESET_BY int_clr_cntrs;
NODE c3_04 CLOCKED_BY /c3_03 RESET_BY int_clr_cntrs;
NODE c3_05 CLOCKED_BY /c3_04 RESET_BY int_clr_cntrs;
NODE c3_06 CLOCKED_BY /c3_05 RESET_BY int_clr_cntrs;
NODE c3_07 CLOCKED_BY /c3_06 RESET_BY int_clr_cntrs;
NODE c3_08 CLOCKED_BY /c3_07 RESET_BY int_clr_cntrs;
NODE c3_09 CLOCKED_BY /c3_08 RESET_BY int_clr_cntrs;
NODE c3_10 CLOCKED_BY /c3_09 RESET_BY int_clr_cntrs;
NODE c3_11 CLOCKED_BY /c3_10 RESET_BY int_clr_cntrs;
NODE c3_12 CLOCKED_BY /c3_11 RESET_BY int_clr_cntrs;
NODE c3_13 CLOCKED_BY /c3_12 RESET_BY int_clr_cntrs;
NODE c3_14 CLOCKED_BY /c3_13 RESET_BY int_clr_cntrs;
NODE c3_15 CLOCKED_BY /c3_14 RESET_BY int_clr_cntrs; "Counter 3
 
NODE c4_00 CLOCKED_BY clk_c4_a RESET_BY int_clr_cntrs;
NODE c4_01 CLOCKED_BY /c4_00 RESET_BY int_clr_cntrs;
NODE c4_02 CLOCKED_BY /c4_01 RESET_BY int_clr_cntrs;
NODE c4_03 CLOCKED_BY /c4_02 RESET_BY int_clr_cntrs;
NODE c4_04 CLOCKED_BY /c4_03 RESET_BY int_clr_cntrs;
NODE c4_05 CLOCKED_BY /c4_04 RESET_BY int_clr_cntrs;
NODE c4_06 CLOCKED_BY /c4_05 RESET_BY int_clr_cntrs;
NODE c4_07 CLOCKED_BY /c4_06 RESET_BY int_clr_cntrs;
NODE c4_08 CLOCKED_BY /c4_07 RESET_BY int_clr_cntrs;
NODE c4_09 CLOCKED_BY /c4_08 RESET_BY int_clr_cntrs;
NODE c4_10 CLOCKED_BY /c4_09 RESET_BY int_clr_cntrs;
NODE c4_11 CLOCKED_BY /c4_10 RESET_BY int_clr_cntrs;
NODE c4_12 CLOCKED_BY /c4_11 RESET_BY int_clr_cntrs;
NODE c4_13 CLOCKED_BY /c4_12 RESET_BY int_clr_cntrs;
NODE c4_14 CLOCKED_BY /c4_13 RESET_BY int_clr_cntrs;
NODE c4_15 CLOCKED_BY /c4_14 RESET_BY int_clr_cntrs; "Counter 4
 
NODE c5_00 CLOCKED_BY clk_c5_a RESET_BY int_clr_cntrs;
NODE c5_01 CLOCKED_BY /c5_00 RESET_BY int_clr_cntrs;
NODE c5_02 CLOCKED_BY /c5_01 RESET_BY int_clr_cntrs;
NODE c5_03 CLOCKED_BY /c5_02 RESET_BY int_clr_cntrs;
NODE c5_04 CLOCKED_BY /c5_03 RESET_BY int_clr_cntrs;
NODE c5_05 CLOCKED_BY /c5_04 RESET_BY int_clr_cntrs;
NODE c5_06 CLOCKED_BY /c5_05 RESET_BY int_clr_cntrs;
NODE c5_07 CLOCKED_BY /c5_06 RESET_BY int_clr_cntrs;
NODE c5_08 CLOCKED_BY /c5_07 RESET_BY int_clr_cntrs;
NODE c5_09 CLOCKED_BY /c5_08 RESET_BY int_clr_cntrs;
NODE c5_10 CLOCKED_BY /c5_09 RESET_BY int_clr_cntrs;
NODE c5_11 CLOCKED_BY /c5_10 RESET_BY int_clr_cntrs;
NODE c5_12 CLOCKED_BY /c5_11 RESET_BY int_clr_cntrs;
NODE c5_13 CLOCKED_BY /c5_12 RESET_BY int_clr_cntrs;
NODE c5_14 CLOCKED_BY /c5_13 RESET_BY int_clr_cntrs;
NODE c5_15 CLOCKED_BY /c5_14 RESET_BY int_clr_cntrs; "Counter 5
 
 
"************************************************
 
int_clr_cntrs = clr_cntrs * master_clk * wr_ssd + reset;
 
                                          "This only for compiler and ACTEL
                                          "system. It does not chance clr_cntrs
                                          "function, but declares master_clk as
                                          "input. Otherwise master_clk is as
                                          "output always LOW.
 
"************************************************
 
 
clk_c0_a = clk_c0 * /(c0_00*c0_01*c0_02*c0_03*c0_04*c0_05*c0_06*c0_07
                     *c0_08*c0_09*c0_10*c0_11*c0_12*c0_13*c0_14*c0_15);
 
clk_c1_a = clk_c1 * /(c1_00*c1_01*c1_02*c1_03*c1_04*c1_05*c1_06*c1_07
                     *c1_08*c1_09*c1_10*c1_11*c1_12*c1_13*c1_14*c1_15);
 
clk_c2_a = clk_c2 * /(c2_00*c2_01*c2_02*c2_03*c2_04*c2_05*c2_06*c2_07
                     *c2_08*c2_09*c2_10*c2_11*c2_12*c2_13*c2_14*c2_15);
 
clk_c3_a = clk_c3 * /(c3_00*c3_01*c3_02*c3_03*c3_04*c3_05*c3_06*c3_07
                     *c3_08*c3_09*c3_10*c3_11*c3_12*c3_13*c3_14*c3_15);
 
clk_c4_a = clk_c4 * /(c4_00*c4_01*c4_02*c4_03*c4_04*c4_05*c4_06*c4_07
                     *c4_08*c4_09*c4_10*c4_11*c4_12*c4_13*c4_14*c4_15);
 
clk_c5_a = clk_c5 * /(c5_00*c5_01*c5_02*c5_03*c5_04*c5_05*c5_06*c5_07
                     *c5_08*c5_09*c5_10*c5_11*c5_12*c5_13*c5_14*c5_15);
 
                         "Overflow control
 
 
"************************************************
 
 
c0_00 = /c0_00;
c0_01 = /c0_01;
c0_02 = /c0_02;
c0_03 = /c0_03;
c0_04 = /c0_04;
c0_05 = /c0_05;
c0_06 = /c0_06;
c0_07 = /c0_07;
c0_08 = /c0_08;
c0_09 = /c0_09;
c0_10 = /c0_10;
c0_11 = /c0_11;
c0_12 = /c0_12;
c0_13 = /c0_13;
c0_14 = /c0_14;
c0_15 = /c0_15;                        "Counter 0
 
c1_00 = /c1_00;
c1_01 = /c1_01;
c1_02 = /c1_02;
c1_03 = /c1_03;
c1_04 = /c1_04;
c1_05 = /c1_05;
c1_06 = /c1_06;
c1_07 = /c1_07;
c1_08 = /c1_08;
c1_09 = /c1_09;
c1_10 = /c1_10;
c1_11 = /c1_11;
c1_12 = /c1_12;
c1_13 = /c1_13;
c1_14 = /c1_14;
c1_15 = /c1_15;                        "Counter 1
 
c2_00 = /c2_00;
c2_01 = /c2_01;
c2_02 = /c2_02;
c2_03 = /c2_03;
c2_04 = /c2_04;
c2_05 = /c2_05;
c2_06 = /c2_06;
c2_07 = /c2_07;
c2_08 = /c2_08;
c2_09 = /c2_09;
c2_10 = /c2_10;
c2_11 = /c2_11;
c2_12 = /c2_12;
c2_13 = /c2_13;
c2_14 = /c2_14;
c2_15 = /c2_15;                        "Counter 2
 
c3_00 = /c3_00;
c3_01 = /c3_01;
c3_02 = /c3_02;
c3_03 = /c3_03;
c3_04 = /c3_04;
c3_05 = /c3_05;
c3_06 = /c3_06;
c3_07 = /c3_07;
c3_08 = /c3_08;
c3_09 = /c3_09;
c3_10 = /c3_10;
c3_11 = /c3_11;
c3_12 = /c3_12;
c3_13 = /c3_13;
c3_14 = /c3_14;
c3_15 = /c3_15;                        "Counter 3
 
c4_00 = /c4_00;
c4_01 = /c4_01;
c4_02 = /c4_02;
c4_03 = /c4_03;
c4_04 = /c4_04;
c4_05 = /c4_05;
c4_06 = /c4_06;
c4_07 = /c4_07;
c4_08 = /c4_08;
c4_09 = /c4_09;
c4_10 = /c4_10;
c4_11 = /c4_11;
c4_12 = /c4_12;
c4_13 = /c4_13;
c4_14 = /c4_14;
c4_15 = /c4_15;                        "Counter 4
 
c5_00 = /c5_00;
c5_01 = /c5_01;
c5_02 = /c5_02;
c5_03 = /c5_03;
c5_04 = /c5_04;
c5_05 = /c5_05;
c5_06 = /c5_06;
c5_07 = /c5_07;
c5_08 = /c5_08;
c5_09 = /c5_09;
c5_10 = /c5_10;
c5_11 = /c5_11;
c5_12 = /c5_12;
c5_13 = /c5_13;
c5_14 = /c5_14;
c5_15 = /c5_15;                        "Counter 5
 
 
"************************************************
 
 
CASE sel_cntr
 
  WHEN 0 =>          ds_i = [c0_15,c0_14,c0_13,c0_12,c0_11,c0_10,c0_09,c0_08,
                             c0_07,c0_06,c0_05,c0_04,c0_03,c0_02,c0_01,c0_00];
 
  WHEN 1 =>          ds_i = [c1_15,c1_14,c1_13,c1_12,c1_11,c1_10,c1_09,c1_08,
                             c1_07,c1_06,c1_05,c1_04,c1_03,c1_02,c1_01,c1_00];
 
  WHEN 2 =>          ds_i = [c2_15,c2_14,c2_13,c2_12,c2_11,c2_10,c2_09,c2_08,
                             c2_07,c2_06,c2_05,c2_04,c2_03,c2_02,c2_01,c2_00];
 
  WHEN 3 =>          ds_i = [c3_15,c3_14,c3_13,c3_12,c3_11,c3_10,c3_09,c3_08,
                             c3_07,c3_06,c3_05,c3_04,c3_03,c3_02,c3_01,c3_00];
 
  WHEN 4 =>          ds_i = [c4_15,c4_14,c4_13,c4_12,c4_11,c4_10,c4_09,c4_08,
                             c4_07,c4_06,c4_05,c4_04,c4_03,c4_02,c4_01,c4_00];
 
  WHEN 5 =>          ds_i = [c5_15,c5_14,c5_13,c5_12,c5_11,c5_10,c5_09,c5_08,
                             c5_07,c5_06,c5_05,c5_04,c5_03,c5_02,c5_01,c5_00];
 
  ELSE               ds_i = .Z.;  "Output Z for counters 6 and 7
 
END CASE;
 